Friday, August 31, 2007

AMD's new Rapid Virtualization Indexing Processors:

Read the full article here.

This is what I'd like to talk about: Memory hardware assists. With the new code-named Barcelona quad-core CPU due to be available in a few weeks with volume shipments in a few months, AMD is going to provide support for what they refer to as "Nested Page Tables" (or NPT for short) which is nothing but memory virtualization support.
A year ago at VMworld 2007 Sr Director R&D Jack Lo provided an illuminating session on the matter: VMware and Hardware Assist Technology (Intel-VT and AMD-V). This session provided a very interesting inside about the mechanisms that VMware is using today in terms of memory virtualization (i.e. Shadow Page Tables) that are basically a software "fake" that allows Guest OS'es to pretend to have full control of the memory address space provided to them while in reality it is the hypervisor maintaining full control of that. In fact if you think about it, in a standard x86 world, only one OS could run on the system and it is that OS keeping control of the hardware resources. In a virtual environment this stack is "screwed up" since the OS doesn't run on real hardware (and there are many OS'es running on the system) so the hypervisor needs to create this software re-mapping of physical resources into the Guest space. Mr. Lo also touched on future hardware assist technologies that should provide a performance boost in this area and AMD NPT was in fact mentioned. The good thing is that "future" at some point becomes "present" and here we are.

The whole idea is that now the processor itself can keep track of these two levels of memory space (i.e. the one that the hypervisor sees and the one that each guest OS sees) without any sort of software remapping being done within the hypervisor as it is the CPU that is able to maintain these multiple mappings onto the registries built into the silicon. What VMware has been suggesting lately is that while their "software binary translation" has better performance than the silicon counterpart Intel-VT and AMD-V for CPU operations, these Nested Page Tables will give a performance boost comparing to their own "software shadow page tables" for memory operations. Without getting into the specifics you should rest assured that VMware is going to intercept NPT support in future releases of the hypervisor in a timely manner. And no, if you were wondering, ESX 3.0.2 (which is the current version as of today) won’t support NPT.

So when is this supposed to show big improvements? As always for performance related things it really depends on what you are doing. For the vast majority of CPU intensive and/or IO intensive workloads NPT won't make much of a difference. There are however some workloads that might gain huge performance benefits. Typically these applications are those with specific memory patterns. This does not necessarily mean virtual machines with big memory footprints but specifically virtual machines with a very high number of "context switches". A occurs whenever a thread needs to leave control to another thread; at the high-level when this occurs the OS needs to save the volatile state of the exiting thread and load the previously saved volatile state of the next thread to be executed. On a standard physical system this is a procedure that the OS handles with the support of the processor while in a virtual environment the Guest OS tries to do the same but instead of getting hardware support to achieve the context switch the hypervisor traps the request and re-works it to fit into the real system resources (well what happens is more complex but you have got the point). This generates overhead especially if you think that you normally get hundreds if not thousands of context switches per second on a Windows system. NPT is all about getting rid of this software re-mapping and allow a much streamlined path from the Guest to the physical resource without the hypervisor acting as the “man in the middle”.

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